The invention relates to an integrated device formed by the combination of a bipolar transistor and a junction field effect transistor, comprising:
a heavily doped emitter zone of a first conductivity type, PA0 a base zone which is less heavily doped than the former, which is of a second conductivity type opposed to the first type, in which the emitter zone is included, and which comprises a lateral extension forming a gate for the field effect transistor, PA0 a collector zone formed on the one hand by a portion of a weakly doped epitaxial layer of the first conductivity type supported by a weakly doped substrate of the second conductivity type, and on the other hand by a heavily doped buried layer region of the first conductivity type extending below the emitter zone, which device in addition comprises a strongly doped peripheral region of the first conductivity type which surrounds the base zone and its lateral extension at least partly and at a certain distance. PA0 a first insulating layer, PA0 a first field electrode formed by a conductive layer in contact with the lateral extension of the base zone through a first opening in the first insulating layer and extending over the first insulating layer over said adjacent more weakly doped region in the direction of the drain region, and over a distance smaller than half the said lateral distance, PA0 a first part of a second field electrode, conductive and in contact with the drain region through a second opening in the first insulating layer, and extending in lateral direction on the first insulating layer in the direction of the first field electrode over a distance smaller than half the said lateral distance, PA0 a second insulating layer, PA0 and a second part of the second field electrode, conductive and in contact with the first part of this same electrode through an opening in the second insulating layer, and extending laterally on the second insulating layer in the direction of the first field electrode at least up to close to this first electrode.
A device of this type is known from the U.S. Pat. No. 4,835,596. This document states that a breakdown voltage of the output electrode of the device of the order of 40 to 60 V may be obtained with the structure described.
However, it is well known that the performance levels required for integrated devices at ever increasing frequencies lead to the use of ever thinner epitaxial layers, at present of the order of no more than 1 to 1.5 .mu.m. Accordingly, the thicknesses of the active zones present in the epitaxial layer are also very small, which results in a reduction in the breakdown voltage BV.sub.CEO of conventional NPN transistors, for example, to 7 V for a process used at present.
In these circumstances, the known device has a reduced performance level as regards its breakdown voltage, whereas it would be highly desirable if higher breakdown voltages could be achieved.